All-bit flash erase type memories have drawn attention as electrically erasable, programmable read-only memories (E.sup.2 PROM). Recent requirements for such memories are to provide a function for altering data in each of a plurality of memory blocks in units of blocks. For example a 4M bit device is divided into 16 blocks each having 32K bytes or into 4 blocks each having 256K bytes, and data erasure is required to be performed on the blocks per unit basis. With such block division of a cell array, cells in a plurality of different blocks are connected to the same word line or data line. Therefore, repeating write/erase of a particular block may apply stress to cells in other non-selected blocks.
The degree of such stress will be discussed for cells of two-layered structure. In the case of cells of two-layered structure used in a flash type E.sup.2 PROM, data write is performed in a manner similar to EPROM. Namely, a control gate is applied with V.sub.CG =12 V, a drain with V.sub.D =6 V, and a source with V.sub.S =O V. In this state, hot electrons generated by an avalanche effect are injected to the floating gate. For data erase, the control gate is applied with V.sub.CG =0 V, the source with V.sub.S =12 V. In this state, electrons are taken out of the floating gate as F-N tunnel current between the floating gate and source.
The characteristic structure of such a cell resides in that the gate oxide film under the floating gate is about 100 angstroms thinner than that of an EPROM cell because a tunnel current flows between the floating gate and source during data erase, and that the superposing area of the source n.sup.+ region and the floating gate is made wider than that of EPROM.
In a cell array having a plurality of blocks comprised by cells of such structure, stress applied to a cell in an erase state or write state in a non-selected block is shown in Table 1. A cell in an erase state in a non-selected block connected to a selected word line is applied to an electric field of about 7.5 MV/cm between its floating gate and source, and a cell in a write state in a non-selected block connected to a selected data line is applied to an electric field of about 6.5 MV/cm between its floating gate and drain.
TABLE 1 __________________________________________________________________________ Control Floating Gate Drain Source Gate Stress Potential Voltage Voltage Voltage Voltage Difference V.sub.CG V.sub.D V.sub.S V.sub.FG V.sub.FG - V.sub.D V.sub.FG - V.sub.S __________________________________________________________________________ Cell in Erase State 0 V 0 V 0 V 1 V -- -- Cell in Write State 0 V 0 V 0 V -1.2 V -- -- Non-selected Block Erase cell 12 V Open 0 V 7.4 V -- 7.4 V Same Word Line Write cell 12 V Open 0 V 5.2 V -- 5.2 V Non-selected Block Erase cell 0 V 6 V 0 V 3.2 V 2.8 V -- Same Data Line Write cell 0 V 6 V 0 V -0.4 V 6.4 V -- __________________________________________________________________________
Next, there will be discussed the time period while stress is applied to a cell in a non-selected block during data erase or data write. Consider a 4M bit device divided into blocks at intervals of 32K bytes in the data line direction. Assuming that cells in a block are subject to write/erase as many as 10.sup.5 times with a write time of 10 .mu.s and write occurrence frequency of 25 times for each cell, a cell in a non-selected block is applied with V.sub.CG =12 V during the total time period of 800 sec. Stress of 7.5 MV/cm is therefore applied between the floating gate and source during the time period 800 sec, inevitably leading to write error. As an alternate, consider a 4M bit device divided into blocks at intervals of 32K bytes in the word line direction, a cell in a non-selected block is applied with 6 V at its drain during the total time period 6400 sec. Stress of 6.5 MV/cm is therefore applied between the floating gate and drain during the time period 6400 sec, inevitably leading to erase error.
As described above, a conventional device is associated with the problem that as data write and erase are effected to a selected block, data write error and erase error may occur at non-selected blocks.
In a conventional data erase scheme, electrons accumulated in a floating gate FG are emitted toward the source by applying a high voltage to the cell source, as discussed previously. With this scheme, it is unable to use a source voltage equal to or higher than the breakdown voltage of a source junction, there arises some restriction that cell sources are required to be formed separately in order to allow block erase (simultaneous erase of a plurality of cells contained within one block). Another scheme using a negative voltage has been considered which can erase data without applying a high voltage to the cell source. An apparatus performing such scheme is conceptually shown in FIG. 24, and timings of waveforms used by the apparatus are shown in FIG. 25. Table 2 shows examples of voltages set to cells at different modes.
TABLE 2 ______________________________________ Mode Cell WL DL Source ______________________________________ Erase Selected Cell -10 V 3 V 5 V Non-selected Cell 5 V 3 V 5 V Program Selected Cell 12 V 6 V 0 V Read Selected Cell 5 V 1 V 0 V ______________________________________
This scheme is characterized in that a plurality of memory cells connected to one selected word line can be erased at the same time. It is now assumed that a word line WL.sub.1 is selected and another word line WL.sub.2 is not selected in a data erase mode. Specifically, the selected word line WL.sub.1 is applied with a voltage VWL.sub.1 of -10 V, the non-selected word line WL.sub.2 is applied with a voltage VWL.sub.2 of 5 V, a source voltage VS is set to 5 V, and data lines DL.sub.1 and DL.sub.2 are set to a floating state. In this state, memory cells M1 and M2 enter an erase state, and memory cells M3 and M4 enter a non-erase state. In a program mode (in a data write mode), hot electrons are injected into a floating gate FG. In a read mode, a sense amplifier judges whether a selected cell is being turned on (a cell current flows) or off (a cell current will not flow).
The above-described scheme has the following problems. At the non-selected cells M3 and M4 in the erase mode, WL.sub.2 is set to 5 V, VS is set to 5 V, and DL.sub.1 and DL.sub.2 enter the floating state. As a result, the data lines DL.sub.1 and DL.sub.2 are charged via the non-selected cells M3 and M4 up to (5 V-V.sub.th) where V.sub.th is a cell threshold value. A cell current for charging the data lines DL.sub.1 and DL.sub.2 flows in the non-selected cells M3 and M4 during the time period from t.sub.1 to t.sub.2, therefore leading to a possibility of write error at the non-selected cells M3 and M4. Also in the end of erase mode, electric charges used for charging the data lines DL.sub.1 and DL.sub.2 are discharged so that a cell current will flow during the time period from t.sub.3 to t.sub.4, leading to a possibility of write error. In addition, if charge/discharge relative to the source and word lines is carried out rapidly, a peak current will flow which may break wiring material.